DK-DEV-5SGXEA7N【PDF 18/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51002

2014.01.10

Extended LUT Mode

1-9

ALM may be implemented in separate ALMs by the Quartus II software to achieve the best possible

performance. As a device begins to fill up, the Quartus II software automatically uses the full potential of

the Stratix V ALM. The Quartus II Compiler automatically searches for functions using common inputs or

completely independent functions to be placed in one ALM to make efficient use of device resources. In

addition, you can manually control resource use by setting location assignments.

You can implement any six-input function using inputs dataa , datab , datac , datad , and either datae0 and

dataf0 or datae1 and dataf1 . If you use datae0 and dataf0 , the output is either driven to register0 ,

register0 is bypassed, or the output driven to register0 and register0 is bypassed, and the data drives

out to the interconnect using the top set of output drivers as shown in the following figure. If you use datae1

and dataf1 , the output either drives to register1 or bypasses register1 , and drives to the interconnect

using the bottom set of output drivers. The Quartus II Compiler automatically selects the inputs to the LUT.

ALMs in normal mode support register packing.

Figure 1-9: Input Function in Normal Mode

If you use datae1 and dataf1 as inputs to a six-input function, datae0 and dataf0 are available for register

packing.

The dataf1 input is available for register packing only if the six-input function is unregistered.

dataf0

datae0

dataa

datab

datac

datad

6-Input

LUT

D

Q

reg0

To General or

Local Routing

datae1

dataf1

D

Q

These inputs are available

for register packing.

labclk

reg1

Extended LUT Mode

In this mode, if the 7-input function is unregistered, the unused eighth input is available for register packing.

Functions that fit into the template, as shown in the following figure, often appear in designs as “ if-else ”

statements in Verilog HDL or VHDL code.

Figure 1-10: Template for Supported 7-Input Functions in Extended LUT Mode for Stratix V Devices

datae0

datac

dataa

datab

datad

dataf0

datae1

5-Input

LUT

5-Input

LUT

combout0

D

reg0

Q

To General or

Local Routing

dataf1

This input is available

for register packing.

Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices

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